1. Field of the Invention
The present invention relates to a voltage generation circuit for a non-volatile semiconductor memory device. More specifically the invention pertains to a booster circuit that generates a boosted voltage from a power source voltage according to an operation mode.
2. Description of the Related Art
A semiconductor memory device has a memory cell array, in which multiple memory cells are arranged in a matrix. Data reading, programming or writing, and erasing operations with regard to each memory cell are generally carried out by specifying an address in a row direction and a column direction of the memory cell array.
Regulation of a voltage applied to a signal line in the row direction and to a signal line in the column direction connected to each memory cell enables an access to the memory cell, in order to carry out a predetermined operation out of the data reading, programming, and erasing operations. For selection of a certain memory cell, a specific voltage, which is different from a voltage applied to the other memory cells, is generated from a power source voltage and is applied to the certain memory cell.
Recently developed MONOS (Metal Oxide Nitride Oxide Semiconductor or Substrate)-type non-volatile semiconductor memory devices are non-volatile and enable electrical erasing of data. In the MONOS-type non-volatile semiconductor memory device, each memory cell has two memory elements as discussed in a reference Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
As described in this cited reference, in order to gain access to the respective memory elements in such a MONOS-type non-volatile semiconductor memory device, it is required to set, as control voltages, a plurality of different voltages corresponding to the respective signal lines (control lines), which depend upon the number of the memory cells. Different control voltages are also required corresponding to respective operation modes (reading, programming, erasing, and standby modes) with regard to each memory element.
A voltage generation circuit generates such a control voltage. The voltage generation circuit typically includes a booster circuit that boosts the power source voltage according to each of diverse operation modes, and a control voltage generation circuit that receives the boosted voltage and generates a plurality of different control voltages required for the respective operation modes.
FIG. 8 shows the structure of a prior art booster circuit 260. The booster circuit 260 includes an oscillation circuit 300 that carries out an oscillating operation and outputs a clock signal OSCK, a charge pump circuit 310 that boosts a power source voltage Vdd in response to the clock signal OSCK and outputs a boosted voltage HV, and a level sense circuit 320 that controls the oscillating operation of the oscillation circuit 300 to make the boosted voltage HV equal to a predetermined setting voltage according to each of the operation modes.
The control logic shown in FIG. 8 represents a circuit that generates and outputs control signals to a diversity of circuits including the booster circuit 260.
The booster circuit 260 shown in FIG. 8 boosts one power source voltage Vdd to a plurality of different voltages. The booster circuit 260 boosts the power source voltage Vdd of, for example, 1.8 V to a high voltage of 8.0 V and outputs the high voltage of 8.0 V as the boosted voltage HV in a Program (data writing) mode and in an Erase (data erasing) mode, while boosting the power source voltage Vdd to a low voltage of 5.0 V and outputs the low voltage of 5.0 V as the boosted voltage HV in a Read (data reading) mode and in a Standby mode. The Standby mode represents a standby state without any access to the memory element for data reading, data writing, or data erasing. The boosted voltage of 5.0 V in the Standby mode may hereafter be referred to as the standby voltage.
The oscillation circuit 300 outputs the clock signal OSCK, which to be supplied to the charge pump circuit 310, in response to an enable signal ENB from the level sense circuit 320. The oscillation circuit 300 stops the oscillating operation when the enable signal ENB is at a low level (in an inactive state), while starting the oscillating operation when the enable signal ENB is at a high level (in an active state).
The charge pump circuit 310 boosts the power source voltage Vdd in response to the clock signal OSCK supplied from the oscillation circuit 300 and outputs the boosted voltage HV. The charge pump circuit 310 should have a sufficient current capacity to enable the generated voltage to be supplied to a subsequent loading (for example, a memory cell array) in the active operation modes, that is, in the Read mode, in the Program mode, and in the Erase mode.
The level sense circuit 320 determines whether the output voltage (the boosted voltage) HV from the charge pump circuit 310 is higher or lower than the low voltage of 5.0 V in the Standby mode and in the Read mode and is higher or lower than the high voltage of 8.0 V in the Program mode and in the Erase mode, in response to a read signal RD, a programming signal PGM, an erasing signal ERS, and a standby signal STB supplied from the control logic. The level sense circuit 320 then feeds back a detection signal ACT representing the result of the determination as the enable signal ENB to the oscillation circuit 300.
The level sense circuit 320 has a comparator 322. A reference voltage Vrf is input into a negative input terminal (−) of the comparator 322, whereas a detected voltage HVrf, which is part of the boosted voltage HV, is input into a positive input terminal (+) of the comparator 322.
The detected voltage HVrf is obtained by dividing the boosted voltage HV by a first voltage division circuit including a first resistor 324, a second resistor 326, and a first transistor 330 connected thereto in series or by a second voltage division circuit including the first resistor 324, a third resistor 328, and a second transistor 332 connected thereto in series.
An output terminal of an OR gate 334 is connected to a gate input terminal of the first transistor 330. The read signal RD representing the Read mode and the standby signal STB representing the Standby mode are input into an input terminal of the OR gate 334. The first transistor 330 functions as a switch that is turned ON when either one of the read signal RD and the standby signal STB is at the high level (in the active state). Similarly, an output terminal of an OR gate 336 is connected to a gate input terminal of the second transistor 332. The programming signal PGM representing the Program mode and the erasing signal ERS representing the Erase mode are input into an input terminal of the OR gate 336. The second transistor 332 functions as a switch that is turned ON when either one of the programming signal PGM and the erasing signal ERS is at the high level (in the active state).
When the read signal RD or the standby signal STB is at the high level (in the active state) to turn the first transistor 330 ON, the boosted voltage HV is divided by means of the first resistor 324 and the second resistor 326 and is input into the comparator 322 as the detected voltage HVrf. When the programming signal PGM or the erasing signal ERS is at the high level (in the active state) to turn the second transistor 332 ON, on the other hand, the boosted voltage HV is divided by means of the first resistor 324 and the third resistor 328 and is input into the comparator 322 as the detected voltage HVrf.
Equations (1) and (2) given below are held on the assumption that the ON resistances of the first and the second transistors 330 and 332 are negligible:HV[low]=Vrf·(1+R1/Rr)  (1)HV[high]=Vrf·(1+R1/Rp)  (2)Here R1, Rr, and Rp respectively denote resistances of the first through the third resistors 324, 326, and 328.
As clearly understood from Equations (1) and (2) given above, the low boosted voltage HV[low] for turning the first transistor 330 ON and the high boosted voltage HV[high] for turning the second transistor 332 ON are independently set by regulating the resistances R1, Rr, and Rp of the first through the third resistors 324, 326, and 328. In this prior art structure, as mentioned previously, the low boosted voltage HV[low] to turn the first transistor 330 ON is set equal to 5.0 V in the Read mode and in the Standby mode. In the Program mode and in the Erase mode, the high boosted voltage HV[high] to turn the second transistor 332 ON is set equal to 8.0 V.
When the boosted voltage HV is higher than the low voltage of 5.0 V in the Read mode or in the Standby mode, the detected voltage HVrf input into the comparator 322 is higher than the reference voltage Vrf. The detection signal ACT output from the level sense circuit 320 is accordingly at the low level. The oscillation circuit 300 receives the detection signal ACT of the low level as the enable signal ENB and stops the oscillating operation.
When the boosted voltage HV is lower than the low voltage of 5.0 V in the Read mode or in the Standby mode, on the contrary, the detected voltage HVrf input into the comparator 322 is lower than the reference voltage Vrf. The detection signal ACT output from the level sense circuit 320 is accordingly at the high level. The oscillation circuit 300 receives the detection signal ACT of the high level as the enable signal ENB and starts the oscillating operation.
In a similar manner, in the Program mode or in the Erase mode, when the boosted voltage HV is higher than the high voltage of 8.0 V, the detected voltage HVrf is higher than the reference voltage Vrf. The detection signal ACT (the enable signal ENB) is accordingly at the low level to stop the oscillating operation in the oscillation circuit 300. When the boosted voltage HV is lower than the high voltage of 8.0 V, on the contrary, the detected voltage HVrf is lower than the reference voltage Vrf. The detection signal ACT (the enable signal ENB) is accordingly at the high level to start the oscillating operation in the oscillation circuit 300.
The feedback circuit including the oscillation circuit 300, the charge pump circuit 310, and the level sense circuit 320 functions to make the detected voltage HVrf equal to the reference voltage Vrf.
In the booster circuit 260, the oscillating operation of the oscillation circuit 300 and thereby the boosting operation of the charge pump circuit 310 are controlled according to the level of the boosted voltage HV detected by the level sense circuit 320. The charge pump circuit 310 is controlled to make the output voltage (boosted voltage) HV from the charge pump circuit 310 equal to the low boosted voltage HV[low] of 5.0 V in the Read mode or in the Standby mode and equal to the high boosted voltage HV[high] of 8.0 V in the Program mode or in the Erase mode.
The control voltage generation circuit included in the voltage generation circuit has a constant voltage circuit, which includes a regulator circuit and a transistor. The constant voltage circuit generates a desired constant voltage from the boosted voltage output from the booster circuit.
FIG. 9 is a circuit diagram showing the structure of a general constant voltage circuit 500 included in the control voltage generation circuit. As shown in FIG. 9, the constant voltage circuit 500 has a transistor Q and a regulator circuit 502 including an operational amplifier OP, a resistance R, and a variable resistance VR.
An input terminal 504 of the constant voltage circuit 500 receives the boosted voltage HV from the booster circuit 260. The reference voltage Vrf, which is input into the negative input terminal (−) of the comparator 322 in the level sense circuit 320 of the booster circuit 260, is also input into a positive input terminal (+) of the operational amplifier OP. An output terminal of the operational amplifier OP is connected to a gate of the p-type MOS transistor Q. The transistor Q has a source connecting with the input terminal 504 and a drain connecting with a negative input terminal (−) of the operational amplifier OP. The drain of the transistor Q is further coupled with a reference potential point via the resistance R and the variable resistance VR.
The transistor Q functions as a variable resistance element, whereas the operational amplifier OP varies the output to make the difference between two inputs equal to 0. The drain voltage of the transistor Q is thus coincident with the reference voltage Vrf. The voltage at an output terminal 508 of the constant voltage circuit 500 is obtained by dividing the reference voltage Vrf by means of the resistance R and the variable resistance VR. A desired constant voltage is generated from the output terminal 508 as the output of the constant voltage circuit 500 by adequately regulating the value of the variable resistance VR.
The prior art voltage generation circuit of the above construction has the problems discussed below at the power supply ON time or at the reset time of the non-volatile semiconductor memory device.
The non-volatile semiconductor memory device is generally in the Standby mode at the power supply ON time or at the reset time. The boosted voltage HV output from the booster circuit 260 is initially at the level of the power source voltage. It is thus required to raise the boosted voltage HV to the level of the standby voltage (5.0 V). In the constant voltage circuit 500 of the control voltage generation circuit that receives the input of the boosted voltage HV, there is a parasitic capacitance hung on the positive input terminal (+) in the operational amplifier OP in the regulator circuit 502, (that is, a parasitic capacitance between the HV input terminal 504 and a Vrf input terminal 506). At the power supply ON time or at the reset time of the non-volatile semiconductor memory device, with an abrupt increase in boosted voltage HV from the power source voltage to the standby voltage in the booster circuit 260, the reference voltage Vrf input into the positive input terminal (+) of the operational amplifier OP may be raised due to the parasitic capacitance.
The reference voltage Vrf is commonly input into the positive input terminal (+) of the operational amplifier OP and into the negative input terminal (−) of the comparator 322 in the level sense circuit 320 of the booster circuit 260, as mentioned previously. Even when the boosted voltage HV reaches the standby voltage (5.0 V), the detected voltage HVrf input into the comparator 322 is still lower than the reference voltage Vrf, which has increased with a rise in boosted voltage HV. The detection signal ACT output from the level sense circuit 320 is then kept at the high level and is input as the enable signal ENB into the oscillation circuit 300. The oscillation circuit 300 accordingly does not stop the oscillating operation but continues oscillation. The boosted voltage HV thus exceeds the standby voltage and continues rising. In the Standby mode at the power supply ON time or at the reset time, it is accordingly difficult to set the boosted voltage HV equal to the standby voltage.